In-Memory Computing Integrated Structure Circuit Based on Nonvolatile Flash Memory Unit

Artificial intelligence has made people’s demands for computer computing efficiency increasingly high. The traditional hardware circuit simulation method neural morphology computation problems of unstable performance and excessive power consumption. This research will use non-volatile flash memory cells that are easy to read write build a convolutional network structure improve the morphological computing. In experiment, floating-gate transistors were used simulate synapses design core cross-array circuits. A voltage subtractor, follower ReLU activation function designed based on differential amplifier. An Iris dataset was introduced in this experiment conduct experiments circuit. IMC high performance, with an accuracy rate 96.2% recall 60.2%. overall current consumption is small, subtractor does not exceed 100 µA, while negative feedback about 440 mA. analog circuits under architecture above 93%, energy only 360 nJ, recognition 12 μs. Compared classic von Neumann architecture, it reduces meeting requirements.